Regviz

Espressif Systems /ESP32-S3 /EXTMEM /DCACHE_TAG_POWER_CTRL

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as DCACHE_TAG_POWER_CTRL

Share

Cut and paste this URL to share the unmodified register and value:

https://regviz.com/r/Espressif Systems/ESP32-S3/EXTMEM/DCACHE_TAG_POWER_CTRL#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (DCACHE_TAG_MEM_FORCE_ON)DCACHE_TAG_MEM_FORCE_ON 0 (DCACHE_TAG_MEM_FORCE_PD)DCACHE_TAG_MEM_FORCE_PD 0 (DCACHE_TAG_MEM_FORCE_PU)DCACHE_TAG_MEM_FORCE_PU

Description

******* Description ***********

Fields

DCACHE_TAG_MEM_FORCE_ON

The bit is used to close clock gating of dcache tag memory. 1: close gating, 0: open clock gating.
DCACHE_TAG_MEM_FORCE_PD

The bit is used to power dcache tag memory down, 0: follow rtc_lslp_pd, 1: power down
DCACHE_TAG_MEM_FORCE_PU

The bit is used to power dcache tag memory up, 0: follow rtc_lslp_pd, 1: power up

Links

()

Register License

Copyright 2024 Espressif Systems (Shanghai) PTE LTD

Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License. You may obtain a copy of the License at

http://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

 ()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data